1. Field of the Invention
The invention relates generally to the fabrication of integrated circuits, and more particularly to a method and resulting structure for forming metal silicide contacts to polycrystalline silicon regions and contacts which are not metal silicides to monocrystalline regions.
2. Description of the Prior Art
Metallization is a critical processing technique throughout the integrated circuit process. It is particularly critical in the formation of electrical contacts to semiconductor regions in silicon integrated circuits in the one micron and submicron feature size era.
Aluminium has found major use as both an electrical contact material to silicon semiconductor regions and as the second or higher level metallurgy in integrated circuits. However, aluminium does have problems particularly as an electrical contact to monocrystalline silicon regions as is well understood by those in the art. One problem is contact resistance, especially in submicrometer contact hole regions.
To overcome these problems of direct aluminum to silicon or aluminum-silicon to silicon electrical contacts the use of a metal silicide layer between these materials have widely begun to be used. Self aligned transition and noble metal silicides of metal such as platinum, palladium, cobalt, nickel, titanium, tantalum, tungsten, etc. have been used. There are problems with this alternative involving metallurgical interaction, consummation of the shallow silicon semiconductor region, junction leakage, etc. The problems have been described in the article by C. Y. Lu et al in IEEE Transaction of Electron Devices Vol. ED-38(2), pp. 246-254, February 1991. Other barrier materials proposed are titanium nitride, titanium carbide, titanium-tungsten, and the like.
Metallic silicides have also been used to improve the conductivity of polycrystalline silicon that is also widely used in integrated circuits. Metal silicides used on polycrystalline silicon, the so called polycide, as gate electrodes, interconnection runners and the like. However, the prize for reduction of polycide resistance versus polysilicon is the difficulty of line width scaling down due to etching profile control problem of polycide structure. The reduction of linewidths and tighter linewidth control is just what is required for the era of one micrometer and submicrometer feature sizes.
It is very difficult to control the linewidth of a polycrystalline silicon metal silicide structure or polycide structure, because its double layer structure is very difficult to pattern especially in the manufacturing environment. The Self Aligned metal siLICIDE or SALICIDE process has been developed to bring more process control. The Salicide process produces simultaneously a metal silicide on the source/drain regions of an MOSFET and the gate electrode of the MOSFET. This process patterns the polycrystalline silicon gate electrode before the metal silicide is formed, so only a single polycrystalline silicon layer needs be etched and the linewidth control is much easier than if a double layer were to be etched.
C. K. Lau U.S. Pat. No. 4,545,116 and F. K. Choi U.S. Pat. No. 4,859,278 describe the use of Salicide processes for contacting both monocrystalline and polycrystalline silicon. These processes illustrate the formation of self aligned metal silicide formation on both forms of silicon simultaneously. In many applications that simultaneous formation is highly advantageous.
There are some applications in one micrometer and submicrometer in both MOSFET and Bipolar technologies where it is desirable to have a thick metal silicide on the gate electrode and interconnection runner level, but without metal silicide on the source/drain or bipolar element level. The reasons for this is for MOSFET integrated circuits that thick metal silicide on the source/drain regions easily causes junction leakage problems which are not compatible with shallow junction requirements for punch through control. The reason for Bipolar integrated circuits is the induced base to collector leakage problem.
It is therefore an object of the invention to provide a method for making MOSFET integrated circuits in the one micrometer and submicrometer feature size era which takes advantage of the Salicide process in linewidth control with metal silicide used at the gate electrode interconnection level and without a metal silicide at the electrical contact to source/drain regions level.
It is a further object of the invention to provide an integrated circuit structure in the one micrometer and submicrometer feature size era which takes advantage of the Salicide process resulting structure in linewidth control with metal silicide used at the second level interconnection, such as buried contact local interconnect as well known by those in the art and without a metal silicide at the electrical contact to semiconductor regions level.